Synchronous Ethernet (SyncE) is an ITU-T standard for computer networking that facilitates the transference of clock signals over the Ethernet physical layer. A main difference between SyncE and “regular” Ethernet has to do with the carrier clock. In SyncE, the carrier clock is synchronized and traceable to a primary reference clock (PRC) whereas with regular Ethernet the carrier clock is a locally generated free running clock. Nonetheless, in both cases, the carrier clock is extracted from data received by the physical layer (PHY). For a phase-locked loop (PLL) device that needs to lock to a SyncE clock, the process is essentially the same as locking to any other telecom-type clock with the frequency being a function of application. The requirements of SyncE with respect to pull-in range, wander/jitter tolerance, wander/jitter generation, etc. are described in a recommendation of the International Telecommunication Union: ITU-T G.8262/Y.1362 2010-07, Timing Characteristics of a Synchronous Ethernet Equipment Slave Clock.
In a strictly SyncE application, there is no need for a 1 pulse-per-second (PPS) signal. Only a digital PLL (DPLL) controls the phase and frequency of the output clocks and frame pulses, if applicable. However, in other applications, a user could require applying a static phase offset to the output clocks and frame pulses in order to trim away delays in a system. This could be a static input-output delay and/or (multiple) output-output delay(s). Because SyncE does not transmit any lower rate frame phase information, it is typically not possible to align frame pulses and timing pulses across a network using just SyncE.
IEEE 1588 is a standard that defines the distribution of timing over packet based networks. As will be understood by those skilled in the art, the timing is no longer carried by a physical clock. Instead, timestamps are sent back and forth between a server (e.g., master) and a client (e.g., slave). The timestamps from the server are linked to the PRC (Cesium, Rubidium, GPS, etc.), whereas the timestamps of the client are linked to the clock recovered by the client (e.g., from packet data). In particular, the client can extract the timing from a collection of received and locally generated timestamps using, for example, an algorithm running on a microprocessor at the client. The algorithm drives a digitally-controlled oscillator (DCO) that then generates the physical clock and 1PPS timing pulse. Ideally, the 1PPS timing pulse generated by the client is phase aligned with the 1PPS signal generated by the server. The algorithm needs to control both the frequency of the output clock(s) and frame/timing pulses as well as the phase of the 1PPS timing pulse. The latter is preferably independent of the output clock frequency notwithstanding the fact that the frequency and phase are hard related to each other. This independence is due to the fact that the phase/position of the 1PPS pulse during the initial snap alignment can be adjusted without changing the frequency and phase of the output clocks.
Using a combination of both SyncE and IEEE 1588 for synchronization typically provides the stability and precision of a physical SyncE clock with the ability to synchronize frame/timing pulses in accordance with IEEE 1588. The SyncE clock and the IEEE 1588 timestamps may or may not be traceable to the same primary timing reference. But, if the SyncE clock and the IEEE 1588 timestamps are traceable to the same primary timing reference, then the SyncE clock can be used for: (i) frequency synchronization of the output clock and the frame/timing pulse; and (ii) phase alignment of the output clock to the input SyncE clock. This can be achieved by the standard function of the PLL, which is the same as in a regular telecom clock (E1, T1, Sonet etc) application. In addition, the IEEE 1588 timestamps can be used to calculate the phase offset between the 1PPS pulse of the server and the 1PPS pulse of the client and then align the two pulses by moving the 1PPS pulse of the client (in phase). The client typically should be able to move the 1PPS pulse by ±0.5 sec.
An alternative way of combining SyncE and IEEE 1588 is by switching back and forth between the two timing references. For this to work, the SyncE clock and the IEEE 1588 timing must be traceable to the same PRC. Initially, a frequency lock is achieved using the SyncE clock as the input reference. Then, the client switches to the IEEE 1588 packet stream as the timing reference. Now the phase of the 1PPS and potentially the output clock pulse is adjusted through the 1PPS coarse alignment and the fine input-output alignment. If the IEEE 1588 timing gets corrupted, then the client makes a hitless reference switch back to the SyncE clock. If the IEEE 1588 timing comes back, the client makes a non-hitless reference switch from the SyncE clock back to the IEEE 1588 timing and gradually pulls-in the phase error from the previous hitless reference switch. Due to the non-zero residual phase error of the hitless reference switching to the SyncE clock, some wander will occur. But the non-hitless reference switch back to the IEEE 1588 timing prevents the accumulation of wander.
Practical implementations of these concepts typically use a digitally-controlled oscillator (DCO) for frequency synthesis and to support IEEE 1588. As illustrated by FIG. 1, a DCO can be set up as an accumulator (e.g., phase accumulator) running at the frequency of the system clock (sysclk). The DCO output clock is very accurate in frequency but may have a pp-jitter of 1 sysclk cycle. Various techniques including the use of a tapped delay line or an analog PLL within a de-jitter circuit can be used to reduce any intrinsic jitter associated with the output of the DCO. The input frequency word to the DCO comes from an IEEE 1588 synchronization algorithm running on an external microprocessor. The 1PPS pulse is divided down from the DCO clock using a counter and comparator logic so that when the counter in incremented to the comparator value, a pulse is generated. The output clock (clk) and 1PPS pulse frequency are directly controlled by the DCO input frequency word.
The phase of the 1PPS pulse can also be adjusted in steps of 1 DCO clock cycle by changing the comparator value, which is shown as: “1PPS phase word”. This technique is fast but provides only relatively coarse phase adjustment, which is often referred to as “snap-alignment.” Moreover, by adjusting the frequency of the DCO, the phase of both the output clock (clk) and 1PPS pulse can be changed. The phase change is the product of the frequency change and the duration of the frequency change. Since the DCO's frequency word has a very fine resolution, the phase of the output clock (clk) and 1PPS pulse can be adjusted in very fine steps. However, if the maximum DCO frequency change is limited to 100 ppm, then larger phase changes may require a relatively long adjustment time. For example, a phase change of 0.5 sec may take 0.5/(1×10−4)=5000 sec (i.e., 1:23 hr). For smaller fine resolution phase changes, temporarily changing the DCO frequency is typically a good method.
Because the frequency word comes from a microprocessor with relatively inaccurate timing, an internal hardware based timer should be incorporated to ensure that the frequency change is applied for a precise duration. In some cases, an internal timer can be used to update the DCO frequency word (from a register) every 100 ms. This internal timer must be running on the same clock that is the system/master clock of the DCO. With a DCO frequency resolution of 1×10−11, phase adjustments with a resolution of 1 ps can be made. If the timer also generates an interrupt to the microprocessor every 100 ms, then the microprocessor can readily synchronize to the DCO. Alternatively, if the 1PPS pulse is generated by a DPLL, which is locked to a (SyncE) reference clock instead of just a DCO, then the phase of the 1PPS pulse can be changed by simply adding an input-to-output phase offset to the DPLL. This will also adjust the phase of both the output clock and the 1PPS pulse.
FIG. 2 illustrates a block diagram of a circuit containing a DPLL core and divider for synchronizing an output clock signal (clk) to a SyncE network clock (i.e., clk is phase aligned and frequency locked to the SyncE clk). But, this circuit does not provide alignment of frame or timing pulses. In contrast, FIG. 3 shows an application diagram for synchronization to an IEEE 1588 packet stream. An external processor runs an algorithm and updates a frequency offset register of the DPLL. As a result, the output clock (clk) and timing pulse (1PPS) are frequency locked to the timing server and the timing pulse is phase aligned to the 1PPS timing pulse of the server.
FIG. 4 illustrates a block diagram of a circuit that supports synchronization to both a SyncE clock and an IEEE 1588 packet stream, which are traceable to the same PRC. The illustrated DPLL core locks to the SyncE clock, and the output clock (clk) and timing pulse (1PPS) are frequency locked to the SyncE clock. An external processor runs an algorithm and updates the phase alignment of the 1PPS pulse. The “coarse” phase alignment is in steps of −0.6 ns. If a finer alignment is needed, then the input-output phase offset adjustment can be used to fine tune the 1PPS and clock phase. This setup can be used when no separate timing paths are required for the SyncE output clock and an IEEE 1588 clock and 1PPS. Ideally, the algorithm adjusts the 1PPS pulses and possibly the output clock phase once, upon initialization, and the DPLL maintains alignment by tracking the input SyncE clock.
These above-described scenarios advantageously require the use of only one DPLL core, but are limited by the requirement that the SyncE clock and the IEEE 1588 timestamps should be traceable to the same primary timing reference. Thus, there continues to be a need for alternative ways of combining SyncE and IEEE 1588 when the SyncE clock and timestamps are not traceable to the same PRC.